| Copyright | (c) Matthew Naylor 2019 (c) Alexandre Joannou 2019-2021 |
|---|---|
| License | MIT |
| Maintainer | mattfn@gmail.com |
| Stability | experimental |
| Safe Haskell | Safe-Inferred |
| Language | GHC2021 |
Blarney.Queue
Description
Synopsis
- data Queue a = Queue {}
- makeQueue :: Bits a => Module (Queue a)
- makeSizedQueue :: Bits a => Int -> Module (Queue a)
- data SizedQueueConfig a = SizedQueueConfig {
- sizedQueueLogSize :: Int
- sizedQueueBuffer :: Module (Queue a)
- makeSizedQueueConfig :: Bits a => SizedQueueConfig a -> Module (Queue a)
- makeSizedQueueCore :: Bits a => Int -> Module (Queue a)
- data ShiftQueueMode
- makeShiftQueue :: Bits a => Int -> Module (Queue a)
- makePipelineQueue :: Bits a => Int -> Module (Queue a)
- makeShiftQueueCore :: Bits a => ShiftQueueMode -> Int -> Module (Queue a, [Option a])
- makeBypassQueue :: Bits a => Module (Queue a)
- makeSinkBuffer :: Bits a => Module (Queue a) -> Sink a -> Module (Sink a)
Documentation
Queue interface
Constructors
| Queue | |
Instances
makeQueue :: Bits a => Module (Queue a) Source #
A full-throughput 2-element queue implemented using 2 registers:
- No combinatorial paths between sides.
- There's a mux on the enqueue path.
data SizedQueueConfig a Source #
Config options for a sized queue
Constructors
| SizedQueueConfig | |
Fields
| |
makeSizedQueueConfig :: Bits a => SizedQueueConfig a -> Module (Queue a) Source #
Sized queue with config options
makeSizedQueueCore :: Bits a => Int -> Module (Queue a) Source #
This one has no output buffer (low latency, but not great for Fmax)
data ShiftQueueMode Source #
There are modes of operation for the shift queue (below):
- Optimise throughput: full throughput, but there's a combinatorial path between notFull and deq
- Optimise Fmax: no combinatorial paths between sides, but max throughput = N/(N+1), where N is the queue capacity
Constructors
| OptFmax | |
| OptThroughput |
Instances
| Eq ShiftQueueMode # | |
Defined in Blarney.Queue Methods (==) :: ShiftQueueMode -> ShiftQueueMode -> Bool # (/=) :: ShiftQueueMode -> ShiftQueueMode -> Bool # | |
makeShiftQueue :: Bits a => Int -> Module (Queue a) Source #
An N-element queue implemented using a shift register:
- No muxes: input element goes straight to a register and output element comes straight from a register.
- N-cycle latency between enqueuing an element and being able to dequeue it, where N is the queue capacity.
This version optimised for Fmax.
makePipelineQueue :: Bits a => Int -> Module (Queue a) Source #
This version is optimised for throughput