Copyright | (c) Matthew Naylor 2019 (c) Alexandre Joannou 2019-2021 |
---|---|
License | MIT |
Maintainer | mattfn@gmail.com |
Stability | experimental |
Safe Haskell | Safe-Inferred |
Language | GHC2021 |
Blarney.Core.Module
Contents
- Modules and actions
- Lift actions to modules
- Action of doing nothing
- Conditional actions
- Validity of a value
- Variable value (read)
- Variable assignment (write)
- Naming hints
- Registers
- Wires
- Read-Write and Write-Only interfaces
- Register files
- Other actions
- External inputs and outputs
- Add a
BV
as a netlist root - Run a pure module
Description
We split the RTL monad into a Module monad and an Action monad, giving a
more familiar HDL structure in which modules instantiate other modules,
and express behaviour through always
blocks containing actions.
Actions cannot instantiate modules.
Synopsis
- newtype Module a = M {}
- newtype Action a = A {}
- always :: Action a -> Module a
- noAction :: Action ()
- whenAction :: Bit 1 -> Action a -> Action a
- switch :: Bits a => a -> [(a, Action ())] -> Action ()
- (-->) :: a -> b -> (a, b)
- class Valid t where
- class Val v a | v -> a where
- val :: v -> a
- class Assign v where
- withNameHint :: NameHint -> Module a -> Module a
- withName :: String -> Module a -> Module a
- noName :: Module a -> Module a
- data Reg t = Reg {}
- makeReg :: Bits a => a -> Module (Reg a)
- makeRegU :: Bits a => Module (Reg a)
- makeDReg :: Bits a => a -> Module (Reg a)
- data Wire t = Wire {}
- makeWire :: Bits a => a -> Module (Wire a)
- makeWireU :: Bits a => Module (Wire a)
- data ReadWrite a = ReadWrite {
- rwReadVal :: a
- rwWriteVal :: a -> Action ()
- data WriteOnly a = WriteOnly {
- woWriteVal :: a -> Action ()
- data RegFile a d = RegFile {}
- makeRegFileInit :: forall a d. (Bits a, Bits d) => String -> Module (RegFile a d)
- makeRegFile :: forall a d. (Bits a, Bits d) => Module (RegFile a d)
- finish :: Action ()
- display :: Displayable a => a
- display_ :: Displayable a => a
- assert :: Bit 1 -> String -> Action ()
- dynamicAssert :: Bit 1 -> String -> Action ()
- staticAssert :: Bool -> String -> Module ()
- input :: KnownNat n => String -> Module (Bit n)
- inputBV :: String -> Width -> Module BV
- output :: String -> Bit n -> Module ()
- outputBV :: String -> BV -> Module ()
- addRoots :: [BV] -> Module ()
- runPureModule :: Module a -> String -> a
Modules and actions
A module is just a wrapper around the RTL monad
Instances
MonadFail Module # | |
Defined in Blarney.Core.Module | |
MonadFix Module # | |
Defined in Blarney.Core.Module | |
Applicative Module # | |
Functor Module # | |
Monad Module # | |
Interface a => Modular (Module a) # | |
Defined in Blarney.Core.Interface | |
ToNetlist (Module ()) # | Convert Module monad to a netlist |
ToSP (SP t0 t1) t0 t1 # | ToSP instance for StreamProcessor itself |
An action is just a wrapper around the RTL monad
Instances
MonadFix Action # | |
Defined in Blarney.Core.Module | |
Applicative Action # | |
Functor Action # | |
Monad Action # | |
Interface a => Interface (Action a) # | |
Interface a => Method (Action a) # | |
Defined in Blarney.Core.Interface Methods toMethodTerm :: Action a -> IfcTerm Source # fromMethodTerm :: IfcTerm -> Action a Source # toMethodType :: Action a -> IfcType Source # | |
a ~ () => Displayable (Action a) # | Display statement |
When (Bit 1) Action # | Overloaded conditional for actions |
Bits a => IfThenElse (Bit 1) (Action a) # | Overloaded if-then-else |
Defined in Blarney.Core.Module |
Lift actions to modules
Action of doing nothing
Conditional actions
whenAction :: Bit 1 -> Action a -> Action a Source #
Conditional block over actions with return value
Validity of a value
Variable value (read)
class Val v a | v -> a where Source #
Variable value (read)
Instances
Val PulseWire (Bit 1) # |
|
Val (ReadWrite t) t # | |
Defined in Blarney.Core.Module | |
Val (Reg t) t # | |
Defined in Blarney.Core.Module | |
Val (Wire t) t # | |
Defined in Blarney.Core.Module | |
Val (Reg t) t # | Register read and write |
Defined in Blarney.Core.Module | |
Val (Wire t) t # | Wire read and write |
Defined in Blarney.Core.Module |
Variable assignment (write)
Variable assignment (write)
Naming hints
Registers
Blarney's register Module type
Instances
Assign Reg # | |
HasField "val" (Reg t) t # | |
Defined in Blarney.Core.Module | |
Generic (Reg t) # | |
(Interface a, Bits a) => Interface (Reg a) # | |
Val (Reg t) t # | |
Defined in Blarney.Core.Module | |
type Rep (Reg t) # | |
Defined in Blarney.Core.Module type Rep (Reg t) = D1 ('MetaData "Reg" "Blarney.Core.Module" "blarney-0.1.0.0-inplace" 'False) (C1 ('MetaCons "Reg" 'PrefixI 'True) (S1 ('MetaSel ('Just "readReg") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 t) :*: S1 ('MetaSel ('Just "writeReg") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (t -> Action ())))) |
makeDReg :: Bits a => a -> Module (Reg a) Source #
A DReg holds the assigned value only for one cycle. At all other times, it has the given default value.
Wires
Blarney's wire Module type
Constructors
Wire | |
Instances
Assign Wire # | |
HasField "val" (Wire t) t # | |
Defined in Blarney.Core.Module | |
Generic (Wire t) # | |
(Interface a, Bits a) => Interface (Wire a) # | |
Val (Wire t) t # | |
Defined in Blarney.Core.Module | |
type Rep (Wire t) # | |
Defined in Blarney.Core.Module type Rep (Wire t) = D1 ('MetaData "Wire" "Blarney.Core.Module" "blarney-0.1.0.0-inplace" 'False) (C1 ('MetaCons "Wire" 'PrefixI 'True) (S1 ('MetaSel ('Just "readWire") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 t) :*: (S1 ('MetaSel ('Just "writeWire") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (t -> Action ())) :*: S1 ('MetaSel ('Just "active") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (Bit 1))))) |
Read-Write and Write-Only interfaces
Read-Write interface
Constructors
ReadWrite | |
Fields
|
Instances
Assign ReadWrite # | |
HasField "val" (ReadWrite t) t # | |
Defined in Blarney.Core.Module | |
Generic (ReadWrite a) # | |
(Interface a, Bits a) => Interface (ReadWrite a) # | |
Val (ReadWrite t) t # | |
Defined in Blarney.Core.Module | |
type Rep (ReadWrite a) # | |
Defined in Blarney.Core.Module type Rep (ReadWrite a) = D1 ('MetaData "ReadWrite" "Blarney.Core.Module" "blarney-0.1.0.0-inplace" 'False) (C1 ('MetaCons "ReadWrite" 'PrefixI 'True) (S1 ('MetaSel ('Just "rwReadVal") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 a) :*: S1 ('MetaSel ('Just "rwWriteVal") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (a -> Action ())))) |
Write-Only interface
Constructors
WriteOnly | |
Fields
|
Register files
makeRegFileInit :: forall a d. (Bits a, Bits d) => String -> Module (RegFile a d) Source #
Create register file with initial contents
makeRegFile :: forall a d. (Bits a, Bits d) => Module (RegFile a d) Source #
Create uninitialised register file
Other actions
display :: Displayable a => a Source #
Display statement
display_ :: Displayable a => a Source #
Display statement (without new line)
External inputs and outputs
Add a BV
as a netlist root
Run a pure module
runPureModule :: Module a -> String -> a Source #
Run a pure module, i.e. a module that has no side effects. If the module has side effects, raise an error.