Copyright	(c) Matthew Naylor 2019 (c) Alexandre Joannou 2019-2021
License	MIT
Maintainer	mattfn@gmail.com
Stability	experimental
Safe Haskell	Safe-Inferred
Language	GHC2021

Blarney.Core.RTL

Contents

RTL monad
Conditional statements
Block naming statements
Mutable variables: registers and wires
Simulation-time statements
Assertions
External inputs and outputs
Register files
Add netlist roots

Description

The module defines the RTL monad, supporting:

Mutable wires, registers and register files.
Conditional statements.
Simulation-time I/O.
Module input and output declarations.

Synopsis

type RTL = ReaderT RTL_R (StateT RTL_S (WriterT RTL_W Identity))
evalPureRTL :: RTL a -> String -> a
evalRTLRoots :: RTL a -> [BV]
whenRTL :: Bit 1 -> RTL a -> RTL a
ifThenElseRTL :: Bits a => Bit 1 -> RTL a -> RTL a -> RTL a
switch :: Bits a => a -> [(a, RTL ())] -> RTL ()
(-->) :: a -> RTL () -> (a, RTL ())
withNameHint :: NameHint -> RTL a -> RTL a
data Reg a = Reg {
- regId :: VarId
- regVal :: a
}
writeReg :: Bits a => Reg a -> a -> RTL ()
data Wire a = Wire {
- wireId :: VarId
- wireVal :: a
- active :: Bit 1
}
writeWire :: Bits a => Wire a -> a -> RTL ()
makeReg :: Bits a => a -> RTL (Reg a)
makeRegU :: Bits a => RTL (Reg a)
makeDReg :: Bits a => a -> RTL (Reg a)
makeWire :: Bits a => a -> RTL (Wire a)
makeWireU :: Bits a => RTL (Wire a)
class Displayable a where
- disp :: Format -> Format -> a
display :: Displayable a => a
display_ :: Displayable a => a
finish :: RTL ()
assert :: Bit 1 -> String -> RTL ()
input :: KnownNat n => String -> RTL (Bit n)
output :: String -> Bit n -> RTL ()
inputBV :: String -> Width -> RTL BV
outputBV :: String -> BV -> RTL ()
data RegFileRTL a d = RegFileRTL {
- lookupRTL :: a -> d
- updateRTL :: a -> d -> RTL ()
}
makeRegFileInit :: forall a d. (Bits a, Bits d) => String -> RTL (RegFileRTL a d)
makeRegFile :: forall a d. (Bits a, Bits d) => RTL (RegFileRTL a d)
addRoots :: [BV] -> RTL ()

RTL monad

type RTL = ReaderT RTL_R (StateT RTL_S (WriterT RTL_W Identity)) Source #

The RTL monad, for register-transfer-level descriptions

evalPureRTL :: RTL a -> String -> a Source #

evalRTLRoots :: RTL a -> [BV] Source #

Conditional statements

whenRTL :: Bit 1 -> RTL a -> RTL a Source #

RTL conditional block with return value

ifThenElseRTL :: Bits a => Bit 1 -> RTL a -> RTL a -> RTL a Source #

If-then-else statement for RTL

switch :: Bits a => a -> [(a, RTL ())] -> RTL () Source #

RTL switch statement

(-->) :: a -> RTL () -> (a, RTL ()) infixl 0 Source #

Operator for switch statement alternatives

Block naming statements

withNameHint :: NameHint -> RTL a -> RTL a Source #

Set a name hint for an RTL block

Mutable variables: registers and wires

data Reg a Source #

Register variables

Constructors

Reg
Fields regId :: VarId Unique identifier regVal :: a Current register value

Instances

Instances details

Assign Reg #
Instance details Defined in Blarney.Core.Module Methods (<==) :: Bits a => Reg a -> a -> Action () Source #
Val (Reg t) t #	Register read and write
Instance details Defined in Blarney.Core.Module Methods val :: Reg t -> t Source #

writeReg :: Bits a => Reg a -> a -> RTL () Source #

Register assignment

data Wire a Source #

Wire variables

Constructors

Wire
Fields wireId :: VarId Unique identifier wireVal :: a Current wire value active :: Bit 1 Is wire being assigned on this cycle?

Instances

Instances details

Assign Wire #
Instance details Defined in Blarney.Core.Module Methods (<==) :: Bits a => Wire a -> a -> Action () Source #
Val (Wire t) t #	Wire read and write
Instance details Defined in Blarney.Core.Module Methods val :: Wire t -> t Source #

writeWire :: Bits a => Wire a -> a -> RTL () Source #

Wire assignment

makeReg :: Bits a => a -> RTL (Reg a) Source #

Create register with initial value

makeRegU :: Bits a => RTL (Reg a) Source #

Create wire with don't care initial value

makeDReg :: Bits a => a -> RTL (Reg a) Source #

A DReg holds the assigned value only for one cycle. At all other times, it has the given default value.

makeWire :: Bits a => a -> RTL (Wire a) Source #

Create wire with default value

makeWireU :: Bits a => RTL (Wire a) Source #

Create wire with don't care default value

Simulation-time statements

class Displayable a where Source #

To support a display statement with variable number of arguments

Methods

disp :: Format -> Format -> a Source #

Instances

Instances details

a ~ () => Displayable (Action a) #	Display statement
Instance details Defined in Blarney.Core.Module Methods disp :: Format -> Format -> Action a Source #
Displayable (RTL a) #	Base case
Instance details Defined in Blarney.Core.RTL Methods disp :: Format -> Format -> RTL a Source #
(FShow b, Displayable a) => Displayable (b -> a) #	Recursive case
Instance details Defined in Blarney.Core.RTL Methods disp :: Format -> Format -> b -> a Source #