Copyright | (c) Matthew Naylor 2021 |
---|---|
License | MIT |
Maintainer | mattfn@gmail.com |
Stability | experimental |
Safe Haskell | Safe-Inferred |
Language | GHC2021 |
Blarney.QuadPortRAM
Description
Synopsis
- ramQuad :: (Bits a, Bits d) => Maybe String -> (a, a, a, a, d, d, Bit 1, Bit 1, Bit 1, Bit 1) -> (d, d)
- makeQuadRAM :: (Bits a, Bits d) => Module (RAM a d, RAM a d)
- makeQuadRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d, RAM a d)
- makeQuadRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d, RAM a d)
Documentation
ramQuad :: (Bits a, Bits d) => Maybe String -> (a, a, a, a, d, d, Bit 1, Bit 1, Bit 1, Bit 1) -> (d, d) Source #
Uninitialised simple quad-port block RAM. (Same-port read during write: reads "dont care")
makeQuadRAM :: (Bits a, Bits d) => Module (RAM a d, RAM a d) Source #
Create uninitialised quad-port RAM. Two read ports, two write ports.