Copyright	(c) Matthew Naylor 2019 (c) Alexandre Joannou 2019-2021
License	MIT
Maintainer	mattfn@gmail.com
Stability	experimental
Safe Haskell	Safe-Inferred
Language	GHC2021

Blarney.Core.RAM

Contents

Block RAM primitives
Block RAM primitives with byte enables
RTL block RAM interface
RTL block RAM interface with byte enables

Description

Synopsis

ram :: (Bits a, Bits d) => (a, d, Bit 1, Bit 1) -> d
ramInit :: (Bits a, Bits d) => String -> (a, d, Bit 1, Bit 1) -> d
ramDual :: (Bits a, Bits d) => (a, a, d, Bit 1, Bit 1) -> d
ramDualInit :: (Bits a, Bits d) => String -> (a, a, d, Bit 1, Bit 1) -> d
ramTrueDual :: (Bits a, Bits d) => (a, d, Bit 1, Bit 1) -> (a, d, Bit 1, Bit 1) -> (d, d)
ramTrueDualInit :: (Bits a, Bits d) => String -> (a, d, Bit 1, Bit 1) -> (a, d, Bit 1, Bit 1) -> (d, d)
ramBE :: KnownNat be => (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be)
ramInitBE :: KnownNat be => String -> (Bit aw, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be)
ramDualBE :: KnownNat be => (Bit aw, Bit aw, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be)
ramDualInitBE :: KnownNat be => String -> (Bit aw, Bit aw, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be)
ramTrueDualBE :: KnownNat be => (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit (8 * be), Bit (8 * be))
ramTrueDualInitBE :: KnownNat be => String -> (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit (8 * be), Bit (8 * be))
data RAM a d = RAM {
- load :: a -> Action ()
- store :: a -> d -> Action ()
- out :: d
- storeActive :: Bit 1
}
makeRAM :: (Bits a, Bits d) => Module (RAM a d)
makeRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d)
makeRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d)
makeTrueDualRAM :: (Bits a, Bits d) => Module (RAM a d, RAM a d)
makeTrueDualRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d, RAM a d)
makeTrueDualRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d, RAM a d)
makeDualRAM :: (Bits a, Bits d) => Module (RAM a d)
makeDualRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d)
makeDualRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d)
makeDualRAMForward :: (Bits a, Bits d) => Module (RAM a d)
makeDualRAMForwardInit :: (Bits a, Bits d) => String -> Module (RAM a d)
nullRAM :: Bits d => RAM a d
data RAMBE aw dw = RAMBE {
- loadBE :: Bit aw -> Action ()
- storeBE :: Bit aw -> Bit dw -> Bit (8 * dw) -> Action ()
- outBE :: Bit (8 * dw)
- storeActiveBE :: Bit 1
}
makeRAMBE :: _ => Module (RAMBE aw dw)
makeRAMInitBE :: _ => String -> Module (RAMBE aw dw)
makeRAMBECore :: _ => Maybe String -> Module (RAMBE aw dw)
makeTrueDualRAMBE :: _ => Module (RAMBE aw dw, RAMBE aw dw)
makeTrueDualRAMInitBE :: _ => String -> Module (RAMBE aw dw, RAMBE aw dw)
makeTrueDualRAMBECore :: _ => Maybe String -> Module (RAMBE aw dw, RAMBE aw dw)
makeDualRAMBE :: _ => Module (RAMBE aw dw)
makeDualRAMInitBE :: _ => String -> Module (RAMBE aw dw)
makeDualRAMBECore :: _ => Maybe String -> Module (RAMBE aw dw)
makeDualRAMForwardBE :: _ => Module (RAMBE aw dw)
makeDualRAMForwardInitBE :: _ => String -> Module (RAMBE aw dw)
makeDualRAMForwardBECore :: _ => Maybe String -> Module (RAMBE aw dw)
nullRAMBE :: KnownNat (8 * dw) => RAMBE aw dw

Block RAM primitives

ram :: (Bits a, Bits d) => (a, d, Bit 1, Bit 1) -> d Source #

Uninitialised block RAM. (Read during write: reads "dont care")

ramInit :: (Bits a, Bits d) => String -> (a, d, Bit 1, Bit 1) -> d Source #

Initilaised block RAM (contents taken from hex file). (Read during write: reads "dont care")

ramDual :: (Bits a, Bits d) => (a, a, d, Bit 1, Bit 1) -> d Source #

Uninitialised simple dual-port block RAM. (Read during write: reads "dont care")

ramDualInit :: (Bits a, Bits d) => String -> (a, a, d, Bit 1, Bit 1) -> d Source #

Initialised simple dual-port block RAM. (Read during write: reads "dont care")

ramTrueDual :: (Bits a, Bits d) => (a, d, Bit 1, Bit 1) -> (a, d, Bit 1, Bit 1) -> (d, d) Source #

Uninitialised true dual-port block RAM. (Read during write: reads "dont care")

ramTrueDualInit :: (Bits a, Bits d) => String -> (a, d, Bit 1, Bit 1) -> (a, d, Bit 1, Bit 1) -> (d, d) Source #

Block RAM primitives with byte enables

ramBE :: KnownNat be => (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be) Source #

Uninitialised block RAM. (Read during write: reads "dont care")

ramInitBE :: KnownNat be => String -> (Bit aw, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be) Source #

Initilaised block RAM (contents taken from hex file). (Read during write: reads "dont care")

ramDualBE :: KnownNat be => (Bit aw, Bit aw, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be) Source #

Uninitialised block RAM. (Read during write: reads "dont care")

ramDualInitBE :: KnownNat be => String -> (Bit aw, Bit aw, Bit (8 * be), Bit 1, Bit 1, Bit be) -> Bit (8 * be) Source #

Initialised block RAM (contents taken from hex file). (Read during write: reads "dont care")

ramTrueDualBE :: KnownNat be => (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit (8 * be), Bit (8 * be)) Source #

Uninitialised true dual-port block RAM. (Read during write: reads "dont care")

ramTrueDualInitBE :: KnownNat be => String -> (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit a, Bit (8 * be), Bit 1, Bit 1, Bit be) -> (Bit (8 * be), Bit (8 * be)) Source #

RTL block RAM interface

data RAM a d Source #

RAM interface

Constructors

RAM
Fields load :: a -> Action () Issue load request store :: a -> d -> Action () Issue store request out :: d Data out storeActive :: Bit 1 Is there a store currently happening?

makeRAM :: (Bits a, Bits d) => Module (RAM a d) Source #

Create uninitialised block RAM

makeRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d) Source #

Create block RAM with initial contents from hex file

makeRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d) Source #

makeTrueDualRAM :: (Bits a, Bits d) => Module (RAM a d, RAM a d) Source #

Create true dual-port block RAM. (Read during write: reads "dont care")

makeTrueDualRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d, RAM a d) Source #

Create true dual-port block RAM with initial contents from hex file. (Read during write: reads "dont care")

makeTrueDualRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d, RAM a d) Source #

makeDualRAM :: (Bits a, Bits d) => Module (RAM a d) Source #

Create uninitialised dual-port RAM. One port used for reading and the other for writing.

makeDualRAMInit :: (Bits a, Bits d) => String -> Module (RAM a d) Source #

Create dual-port RAM with initial contents from hex file. One port used for reading and the other for writing.

makeDualRAMCore :: (Bits a, Bits d) => Maybe String -> Module (RAM a d) Source #

makeDualRAMForward :: (Bits a, Bits d) => Module (RAM a d) Source #

Uninitialised dual-port forwarding block RAM. Read and write to same address yields new data.

makeDualRAMForwardInit :: (Bits a, Bits d) => String -> Module (RAM a d) Source #

Dual-port forwarding block RAM with initial contents from hex file. Read and write to same address yields new data.

nullRAM :: Bits d => RAM a d Source #

RAM interface with no backing functionality

RTL block RAM interface with byte enables

data RAMBE aw dw Source #

RAM (with byte enables) interface (data width is in bytes)

Constructors

RAMBE
Fields loadBE :: Bit aw -> Action () Issue load request storeBE :: Bit aw -> Bit dw -> Bit (8 * dw) -> Action () Issue store request, with byte enables outBE :: Bit (8 * dw) Data out storeActiveBE :: Bit 1 Is there a store currently happening?

makeRAMBE :: _ => Module (RAMBE aw dw) Source #

Create uninitialised block RAM with byte enables

makeRAMInitBE :: _ => String -> Module (RAMBE aw dw) Source #

Create block RAM with byte enables and initial contents from hex file

makeRAMBECore :: _ => Maybe String -> Module (RAMBE aw dw) Source #

makeTrueDualRAMBE :: _ => Module (RAMBE aw dw, RAMBE aw dw) Source #

Create true dual-port block RAM with byte enables (Read during write: reads "dont care")

makeTrueDualRAMInitBE :: _ => String -> Module (RAMBE aw dw, RAMBE aw dw) Source #

Create true dual-port block RAM with byte enables and initial contents from hex file (Read during write: reads "dont care")

makeTrueDualRAMBECore :: _ => Maybe String -> Module (RAMBE aw dw, RAMBE aw dw) Source #

makeDualRAMBE :: _ => Module (RAMBE aw dw) Source #

Create uninitialised dual-port RAM with byte enables. One port used for reading and the other for writing.

makeDualRAMInitBE :: _ => String -> Module (RAMBE aw dw) Source #

Create dual-port RAM with byte enables and initial contents from hex file. One port used for reading and the other for writing.

makeDualRAMBECore :: _ => Maybe String -> Module (RAMBE aw dw) Source #

makeDualRAMForwardBE :: _ => Module (RAMBE aw dw) Source #

Create uninitialised forwarding dual-port RAM with byte enables. One port used for reading and the other for writing. Read-during-write yields new data.

makeDualRAMForwardInitBE :: _ => String -> Module (RAMBE aw dw) Source #

Create forwarding dual-port RAM with byte enables and initial contents from hex file. One port used for reading and the other for writing. Read-during-write yields new data.

makeDualRAMForwardBECore :: _ => Maybe String -> Module (RAMBE aw dw) Source #

nullRAMBE :: KnownNat (8 * dw) => RAMBE aw dw Source #

RAMBE interface with no backing functionality