Copyright	(c) Matthew Naylor 2019 (c) Alexandre Joannou 2019-2021
License	MIT
Maintainer	mattfn@gmail.com
Stability	experimental
Safe Haskell	Safe-Inferred
Language	GHC2021

Blarney.Backend.Verilog

Description

Convert Blarney Netlist to Verilog modules.

Synopsis

genVerilogModule :: Netlist -> String -> String -> IO ()
genVerilogTop :: Netlist -> String -> String -> IO ()

Documentation

genVerilogModule Source #

Arguments

:: Netlist	Blarney netlist
-> String	Module name
-> String	Output directory
-> IO ()

Convert given Blarney Netlist to a Verilog module

genVerilogTop Source #

Arguments

:: Netlist	Blarney module
-> String	Top-level module name
-> String	Output directory
-> IO ()

Convert given Blarney Netlist to a top-level Verilog module, and automatically generate a sample verilator wrapper and makefile too. This is useful for simple examples and projects. Most projects will probably require a more customised verilator wrapper; in that case, just use genVerilogModule, even for the top-level module.