| Copyright | (c) Matthew Naylor 2019 (c) Alexandre Joannou 2019-2021 |
|---|---|
| License | MIT |
| Maintainer | mattfn@gmail.com |
| Stability | experimental |
| Safe Haskell | Safe-Inferred |
| Language | GHC2021 |
Blarney.Core.BV
Description
This module represents the core of the Blarney HDL, upon which all hardware description features are built. It provides untyped bit vectors, i.e. bit vectors whose width is not specified in the type. Hardware developers should not use these untyped primitives directly (unless they know what they are doing), because width-mistmatches are not checked. Any bit-vector can be evaluated symbolically, using a feature similar to Observable Sharing [1], to produce a netlist, i.e. a graph whose nodes are primitive component instances and whose edges are connections.
- K. Claessen, D. Sands. Observable Sharing for Functional Circuit Description, ASIAN 1999.
Synopsis
- data BV = BV {
- bvPrim :: Prim
- bvInputs :: [BV]
- bvOutput :: OutputName
- bvNameHints :: NameHints
- bvInstId :: InstId
- makePrim :: Prim -> [BV] -> [OutputName] -> [BV]
- makePrim0 :: Prim -> [BV] -> BV
- makePrim1 :: Prim -> [BV] -> BV
- constBV :: Width -> Integer -> BV
- dontCareBV :: Width -> BV
- addBV :: BV -> BV -> BV
- subBV :: BV -> BV -> BV
- mulBV :: BV -> BV -> BV
- fullMulBV :: Bool -> BV -> BV -> BV
- divBV :: BV -> BV -> BV
- modBV :: BV -> BV -> BV
- invBV :: BV -> BV
- andBV :: BV -> BV -> BV
- orBV :: BV -> BV -> BV
- xorBV :: BV -> BV -> BV
- leftBV :: BV -> BV -> BV
- rightBV :: BV -> BV -> BV
- arithRightBV :: BV -> BV -> BV
- equalBV :: BV -> BV -> BV
- notEqualBV :: BV -> BV -> BV
- lessThanBV :: BV -> BV -> BV
- lessThanEqBV :: BV -> BV -> BV
- replicateBV :: Int -> BV -> BV
- zeroExtendBV :: OutputWidth -> BV -> BV
- signExtendBV :: OutputWidth -> BV -> BV
- selectBV :: (BitIndex, BitIndex) -> BV -> BV
- concatBV :: BV -> BV -> BV
- muxBV :: BV -> [BV] -> BV
- idBV :: BV -> BV
- testPlusArgsBV :: String -> BV
- inputPinBV :: Width -> String -> BV
- regBV :: Width -> BV -> BV -> BV
- regEnBV :: Width -> BV -> BV -> BV -> BV
- mergeWritesBV :: MergeStrategy -> Width -> [(BV, BV)] -> BV
- regFileReadBV :: RegFileInfo -> BV -> BV
- getInitBV :: BV -> InitVal
- ramBV :: OutputWidth -> Maybe String -> (BV, BV, BV, BV, Maybe BV) -> BV
- dualRamBV :: OutputWidth -> Maybe String -> (BV, BV, BV, BV, BV, Maybe BV) -> BV
- trueDualRamBV :: OutputWidth -> Maybe String -> (BV, BV, BV, BV, Maybe BV) -> (BV, BV, BV, BV, Maybe BV) -> (BV, BV)
- bvPrimOutWidth :: BV -> OutputWidth
- lookupParam :: [Param] -> String -> String
- addBVNameHint :: BV -> NameHint -> BV
- addBVNameHints :: BV -> NameHints -> BV
Untyped bit vectors
An untyped bit vector output wire from a primitive component instance
makePrim :: Prim -> [BV] -> [OutputName] -> [BV] Source #
Helper function for creating an instance of a primitive component
Bit-vector primitives
dontCareBV :: Width -> BV Source #
Don't care of given width
fullMulBV :: Bool -> BV -> BV -> BV Source #
Multiplier (full precision, i.e. output width is 2x input width)
zeroExtendBV :: OutputWidth -> BV -> BV Source #
Zero-extend a bit vector
signExtendBV :: OutputWidth -> BV -> BV Source #
Sign-extend a bit vector
testPlusArgsBV :: String -> BV Source #
Test plusargs
regEnBV :: Width -> BV -> BV -> BV -> BV Source #
Register of given width with initial value and enable wire
mergeWritesBV :: MergeStrategy -> Width -> [(BV, BV)] -> BV Source #
Merge a list of inputs together
regFileReadBV :: RegFileInfo -> BV -> BV Source #
Read from register file
getInitBV :: BV -> InitVal Source #
Get the value of a constant bit vector, which may involve bit manipulations. Used to determine the initial value of a register.
ramBV :: OutputWidth -> Maybe String -> (BV, BV, BV, BV, Maybe BV) -> BV Source #
Single-port block RAM. Inputs: address, data, write-enable, read-enable, optional byte-enable
dualRamBV :: OutputWidth -> Maybe String -> (BV, BV, BV, BV, BV, Maybe BV) -> BV Source #
Simple dual-port block RAM. Inputs: read address, write address, data, write-enable, read-enable, optional byte-enable
trueDualRamBV :: OutputWidth -> Maybe String -> (BV, BV, BV, BV, Maybe BV) -> (BV, BV, BV, BV, Maybe BV) -> (BV, BV) Source #
True dual-port block RAM. Inputs (x2): address, data, write-enable, read-enable, optional byte-enable
Other misc helpers
bvPrimOutWidth :: BV -> OutputWidth Source #
helper to get the OutputWidth of the Prim of a BV